feat: 唐磊 hw agent 切换 Vision-Exp 模型
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# 2026-08-24 工作日志
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## 唐磊模型切换 DeepSeek-V4-Flash-Vision-Exp
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- 背景：唐磊（ou_b048b1554913b061ae24ae15a89d6d3b）后续主要做硬件设计、画 PCB，需要看图能力（原理图/PCB/datasheet/封装/波形）
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- 方案：新增 `hw` agent，默认模型 `deepseek/deepseek-v4-flash-vision-exp`（text+image），通过 bindings 把唐磊飞书 DM 精确路由到 hw
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- 路由：`{agentId: hw, match: {channel: feishu, peer: {kind: direct, id: ou_b048b1554913b061ae24ae15a89d6d3b}}}`；main agent 兜底 feishu
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- 模型验证：官方定价与 v4-flash 相同（input $0.22/1M, output $0.66/1M, 1M ctx），实测推理正常
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- 配置备份：~/.openclaw/openclaw.json.bak.vision-*
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- 注意：bindings 是追加到 config 的顶层 key；agents.list 热重载生效，bindings 需配合 openclaw agents list 验证
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#!/usr/bin/env python3
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"""Generate KiCad 7 PCB for the standalone oscillator module (min board).
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Flow: J1(coil) -> TVS1 -> T1 -> Colpitts(Q1+C1/C2/Cc2) -> LM393(U1) -> F_OUT
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Layout: 46x28mm, VCC rail top (y=25.5), GND pour bottom, 2-layer.
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Routing: grid A* router (0.5mm), 0.25mm tracks, 0.2mm clearance.
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"""
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import os, math, heapq, glob
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import pcbnew
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from pcbnew import (VECTOR2I, FromMM, F_Cu, B_Cu, F_SilkS, F_CrtYd,
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Edge_Cuts, PAD_SHAPE_ROUNDRECT, PAD_ATTRIB_SMD)
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BASE = os.path.dirname(os.path.abspath(__file__))
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PCB = os.path.join(BASE, "osc-module.kicad_pcb")
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FP = "/usr/share/kicad/footprints"
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MM = lambda v: int(FromMM(v))
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PX = lambda x, y: VECTOR2I(MM(x), MM(y))
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# ---------------- board ----------------
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board = pcbnew.BOARD()
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ds = board.GetDesignSettings()
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ds.m_MinClearance = MM(0.2)
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ds.m_TrackMinWidth = MM(0.25)
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ds.m_MinThroughDrill = MM(0.4)
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ds.m_ViasMinSize = MM(0.8)
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BOARD_W, BOARD_H = 46.0, 28.0
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# ---------------- nets ----------------
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def make_net(name):
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n = pcbnew.NETINFO_ITEM(board, name)
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board.Add(n)
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return n
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NETS = {}
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for nm in ["COIL_A", "COIL_B", "BASE", "COLLECTOR", "EMITTER",
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"COMP_IN", "VREF", "F_OUT", "VCC", "GND"]:
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NETS[nm] = make_net(nm)
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def nc(nm):
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return NETS[nm].GetNetCode()
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# ---------------- footprints ----------------
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def load_fp(lib, name):
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fp = pcbnew.FootprintLoad(os.path.join(FP, lib), name)
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if fp is None:
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raise RuntimeError(f"footprint not found: {lib}:{name}")
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return fp
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def place(fp, ref, value, x, y, rot=0):
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fp.SetReference(ref)
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fp.SetValue(value)
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fp.SetPosition(PX(x, y))
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fp.SetOrientationDegrees(rot)
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board.Add(fp)
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return fp
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place(load_fp("Connector_PinHeader_2.54mm.pretty", "PinHeader_1x02_P2.54mm_Vertical"),
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"J1", "接线圈", 4.5, 21.5)
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place(load_fp("Diode_SMD.pretty", "D_SOD-123"), "TVS1", "TVS", 9.0, 21.5)
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place(load_fp("Capacitor_SMD.pretty", "C_0603_1608Metric"), "C1", "100~470p", 20.5, 20.0, 180)
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place(load_fp("Package_TO_SOT_SMD.pretty", "SOT-23-3"), "Q1", "S9018", 25.5, 21.5)
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place(load_fp("Capacitor_SMD.pretty", "C_0603_1608Metric"), "Cc2", "10p", 30.5, 20.0)
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place(load_fp("Capacitor_SMD.pretty", "C_0603_1608Metric"), "C2", "100p", 27.5, 23.5, 90)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "Re", "1k", 30.0, 23.5, 90)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "Rb1", "100k", 20.5, 16.5, 180)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "Rb2", "47k", 22.7, 16.5, 180)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "Rc", "2.2k", 29.5, 16.5, 180)
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place(load_fp("Package_SO.pretty", "SOIC-8_3.9x4.9mm_P1.27mm"), "U1", "LM393", 33.0, 6.0)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "R3", "10k", 27.5, 2.0, 90)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "R4", "10k", 29.0, 2.0, 90)
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place(load_fp("Resistor_SMD.pretty", "R_0603_1608Metric"), "R7", "10k上拉", 38.5, 4.5)
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place(load_fp("Connector_PinHeader_2.54mm.pretty", "PinHeader_1x03_P2.54mm_Vertical"),
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"J2", "VCC/GND/F_OUT", 40.5, 6.0)
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# custom T1: 4-pad SMD matching transformer
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t1 = pcbnew.FOOTPRINT(board)
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t1.SetReference("T1")
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t1.SetValue("XFMR 1:1")
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t1.SetPosition(PX(15.0, 21.5))
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for i, (dx, dy) in enumerate([(-2.5, -1.5), (-2.5, 1.5), (2.5, -1.5), (2.5, 1.5)], 1):
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pad = pcbnew.PAD(t1)
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pad.SetName(str(i))
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pad.SetShape(PAD_SHAPE_ROUNDRECT)
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pad.SetSize(PX(1.6, 1.6))
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pad.SetPosition(PX(dx, dy))
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pad.SetLayerSet(pcbnew.PAD_SMD)
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pad.SetAttribute(PAD_ATTRIB_SMD)
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pad.SetRoundRectRadiusRatio(0.25)
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t1.Add(pad)
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for layer, x1, y1, x2, y2 in [(F_CrtYd, -3.4, -2.4, 3.4, 2.4),
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(F_SilkS, -3.0, -2.0, 3.0, 2.0)]:
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s = pcbnew.FP_SHAPE(t1)
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s.SetShape(pcbnew.SHAPE_T_RECT)
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s.SetStart(PX(x1, y1))
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s.SetEnd(PX(x2, y2))
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s.SetLayer(layer)
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s.SetStrokeWidth(MM(0.15))
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t1.Add(s)
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board.Add(t1)
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# mounting holes (2x, non-plated M3)
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holes = [(6.0, 4.0), (42.0, 22.0)]
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for hx, hy in holes:
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name = "MountingHole_3.2mm_M3"
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cand = glob.glob(os.path.join(FP, "MountingHole.pretty", name + ".kicad_mod"))
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if not cand:
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cand = glob.glob(os.path.join(FP, "MountingHole.pretty", "*3.2mm*.kicad_mod"))
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if not cand:
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raise RuntimeError("no mounting hole footprint")
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place(load_fp("MountingHole.pretty", os.path.basename(cand[0])[:-9]),
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"H", "M3", hx, hy)
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# ---------------- pad net map ----------------
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PADMAP = {
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"J1": {"1": "COIL_A", "2": "COIL_B"},
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"TVS1": {"1": "COIL_A", "2": "COIL_B"},
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"T1": {"1": "COIL_A", "2": "COIL_B", "3": "BASE", "4": "GND"},
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"C1": {"1": "BASE", "2": "GND"},
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"Q1": {"1": "BASE", "2": "EMITTER", "3": "COLLECTOR"},
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"Cc2": {"1": "COLLECTOR", "2": "COMP_IN"},
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"C2": {"1": "EMITTER", "2": "GND"},
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"Re": {"1": "EMITTER", "2": "GND"},
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"Rb1": {"1": "BASE", "2": "VCC"},
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"Rb2": {"1": "BASE", "2": "GND"},
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"Rc": {"1": "VCC", "2": "COLLECTOR"},
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"U1": {"1": "F_OUT", "2": "VREF", "3": "COMP_IN", "4": "GND",
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"5": "GND", "6": "GND", "7": "GND", "8": "VCC"},
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"R3": {"1": "VREF", "2": "VCC"},
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"R4": {"1": "GND", "2": "VREF"},
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"R7": {"1": "F_OUT", "2": "VCC"},
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"J2": {"1": "VCC", "2": "GND", "3": "F_OUT"},
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}
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fps = {fp.GetReference(): fp for fp in board.GetFootprints()}
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net_pads = {nm: [] for nm in NETS}
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for ref, pm in PADMAP.items():
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for pname, net in pm.items():
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pad = fps[ref].FindPadByNumber(pname)
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pad.SetNetCode(nc(net))
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pos = pad.GetPosition()
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net_pads[net].append((ref, pname, pos.x, pos.y))
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def mmpos(p):
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return (p.x / 1e6, p.y / 1e6)
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# ---------------- grid A* router ----------------
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GRID = 0.5
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NX = int(BOARD_W / GRID)
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NY = int(BOARD_H / GRID)
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blocked = bytearray(NX * NY)
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def cell(x, y):
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return (int(round(x / GRID)), int(round(y / GRID)))
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def idx(i, j):
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return j * NX + i
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def inb(i, j):
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return 0 <= i < NX and 0 <= j < NY
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def block_circle(cx, cy, r):
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i0, j0 = cell(cx - r, cy - r)
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i1, j1 = cell(cx + r, cy + r)
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for j in range(max(0, j0), min(NY, j1 + 1)):
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for i in range(max(0, i0), min(NX, i1 + 1)):
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dx = i * GRID - cx
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dy = j * GRID - cy
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if dx * dx + dy * dy <= r * r:
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blocked[idx(i, j)] = 1
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def block_rect(x0, y0, x1, y1):
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i0, j0 = cell(x0, y0)
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i1, j1 = cell(x1, y1)
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for j in range(max(0, j0), min(NY, j1 + 1)):
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for i in range(max(0, i0), min(NX, i1 + 1)):
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blocked[idx(i, j)] = 1
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def dist_pt_seg(px, py, x0, y0, x1, y1):
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dx, dy = x1 - x0, y1 - y0
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L2 = dx * dx + dy * dy
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if L2 == 0:
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return math.hypot(px - x0, py - y0)
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t = max(0.0, min(1.0, ((px - x0) * dx + (py - y0) * dy) / L2))
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return math.hypot(px - (x0 + t * dx), py - (y0 + t * dy))
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def block_segment(x0, y0, x1, y1, pad=0.4):
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i0, j0 = cell(min(x0, x1) - pad, min(y0, y1) - pad)
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i1, j1 = cell(max(x0, x1) + pad, max(y0, y1) + pad)
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for j in range(max(0, j0), min(NY, j1 + 1)):
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for i in range(max(0, i0), min(NX, i1 + 1)):
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if dist_pt_seg(i * GRID, j * GRID, x0, y0, x1, y1) <= pad:
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blocked[idx(i, j)] = 1
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# block everything that already exists
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for fp in board.GetFootprints():
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for pad in fp.Pads():
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if not (pad.IsOnLayer(F_Cu) or pad.IsOnLayer(B_Cu)):
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continue
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bb = pad.GetBoundingBox()
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block_rect(bb.GetLeft() / 1e6 - 0.4, bb.GetTop() / 1e6 - 0.4,
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bb.GetRight() / 1e6 + 0.4, bb.GetBottom() / 1e6 + 0.4)
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# board edge margin
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block_rect(-5, -5, 1.2, BOARD_H + 5)
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block_rect(BOARD_W - 1.2, -5, BOARD_W + 5, BOARD_H + 5)
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block_rect(-5, -5, BOARD_W + 5, 1.2)
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block_rect(-5, BOARD_H - 1.2, BOARD_W + 5, BOARD_H + 5)
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for hx, hy in holes:
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block_circle(hx, hy, 2.0)
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tracks = []
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def add_track(x0, y0, x1, y1, net):
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t = pcbnew.PCB_TRACK(board)
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t.SetStart(PX(x0, y0))
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t.SetEnd(PX(x1, y1))
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t.SetWidth(MM(0.25))
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t.SetLayer(F_Cu)
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t.SetNetCode(nc(net))
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board.Add(t)
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tracks.append(t)
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block_segment(x0, y0, x1, y1)
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def unblock_net(net, r=0.45):
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for (ref, pname, x, y) in net_pads[net]:
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block_circle_free(x / 1e6, y / 1e6, r)
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def block_circle_free(cx, cy, r):
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"""unblock cells within r of (cx,cy)"""
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i0, j0 = cell(cx - r, cy - r)
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i1, j1 = cell(cx + r, cy + r)
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for j in range(max(0, j0), min(NY, j1 + 1)):
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for i in range(max(0, i0), min(NX, i1 + 1)):
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dx = i * GRID - cx
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dy = j * GRID - cy
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if dx * dx + dy * dy <= r * r:
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blocked[idx(i, j)] = 0
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def astar(sx, sy, gx, gy):
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si, sj = cell(sx, sy)
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gi, gj = cell(gx, gy)
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if not inb(si, sj) or not inb(gi, gj):
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return None
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if blocked[idx(si, sj)] or blocked[idx(gi, gj)]:
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return None
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open_h = [(0.0, si, sj)]
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g = {(si, sj): 0.0}
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came = {}
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closed = set()
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while open_h:
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f, i, j = heapq.heappop(open_h)
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if (i, j) == (gi, gj):
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path = [(gi, gj)]
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while (i, j) in came:
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(i, j) = came[(i, j)]
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path.append((i, j))
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path.reverse()
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return path
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if (i, j) in closed:
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continue
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closed.add((i, j))
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for di, dj in ((1, 0), (-1, 0), (0, 1), (0, -1)):
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ni, nj = i + di, j + dj
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if not inb(ni, nj) or blocked[idx(ni, nj)]:
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continue
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ng = g[(i, j)] + 1.0
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if (ni, nj) not in g or ng < g[(ni, nj)]:
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g[(ni, nj)] = ng
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came[(ni, nj)] = (i, j)
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heapq.heappush(open_h, (ng + abs(ni - gi) + abs(nj - gj), ni, nj))
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return None
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def path_to_tracks(path, net):
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# merge collinear runs
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runs = []
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cur = [path[0]]
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for p in path[1:]:
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if cur and (p[0] == cur[-1][0] or p[1] == cur[-1][1]):
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cur.append(p)
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else:
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runs.append(cur)
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cur = [p]
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runs.append(cur)
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for run in runs:
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x0, y0 = run[0][0] * GRID, run[0][1] * GRID
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x1, y1 = run[-1][0] * GRID, run[-1][1] * GRID
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if (x0, y0) != (x1, y1):
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add_track(x0, y0, x1, y1, net)
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def route_net(net, order=None):
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pads = [(p[2] / 1e6, p[3] / 1e6) for p in net_pads[net]]
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if order:
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pads = [pads[i] for i in order]
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unblock_net(net)
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cur = pads[0]
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for nxt in pads[1:]:
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path = astar(cur[0], cur[1], nxt[0], nxt[1])
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if path is None:
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print(f"!! A* FAILED: {net} {cur} -> {nxt}")
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return False
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path_to_tracks(path, net)
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cur = nxt
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return True
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# ---- VCC rail (top) ----
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add_track(2.0, 25.5, 44.0, 25.5, "VCC")
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# ---- signal nets ----
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ok = True
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ok &= route_net("COIL_A")
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ok &= route_net("COIL_B")
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ok &= route_net("EMITTER")
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ok &= route_net("COLLECTOR")
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ok &= route_net("BASE")
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ok &= route_net("COMP_IN")
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ok &= route_net("VREF")
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ok &= route_net("F_OUT")
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# ---- VCC drops (chain from rail) ----
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vcc_pads = [(p[2] / 1e6, p[3] / 1e6) for p in net_pads["VCC"]]
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vcc_chain = [(43.0, 25.5)] + vcc_pads + [(3.0, 25.5)]
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unblock_net("VCC")
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cur = vcc_chain[0]
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for nxt in vcc_chain[1:]:
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path = astar(cur[0], cur[1], nxt[0], nxt[1])
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if path is None:
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print(f"!! A* FAILED: VCC {cur} -> {nxt}")
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ok = False
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else:
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path_to_tracks(path, "VCC")
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cur = nxt
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# ---- GND vias + stubs ----
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gnd_vias = []
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for (ref, pname, x, y) in net_pads["GND"]:
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pad = fps[ref].FindPadByNumber(pname)
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if pad.GetAttribute() != PAD_ATTRIB_SMD:
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continue # THT connects to pour through hole
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||||
px, py = x / 1e6, y / 1e6
|
||||
# chain the three unused U1 comparator pads together first
|
||||
vx, vy = None, None
|
||||
for ox, oy in [(1.6, 0), (-1.6, 0), (0, 1.6), (0, -1.6)]:
|
||||
cx0, cy0 = px + ox, py + oy
|
||||
i0, j0 = cell(cx0, cy0)
|
||||
if not inb(i0, j0):
|
||||
continue
|
||||
free = True
|
||||
for j in range(max(0, j0 - 2), min(NY, j0 + 3)):
|
||||
for i in range(max(0, i0 - 2), min(NX, i0 + 3)):
|
||||
if blocked[idx(i, j)]:
|
||||
free = False
|
||||
break
|
||||
if not free:
|
||||
break
|
||||
if free:
|
||||
vx, vy = cx0, cy0
|
||||
break
|
||||
if vx is None:
|
||||
print(f"!! no via spot for GND {ref}.{pname}")
|
||||
ok = False
|
||||
continue
|
||||
via = pcbnew.PCB_VIA(board)
|
||||
via.SetPosition(PX(vx, vy))
|
||||
via.SetDrill(MM(0.4))
|
||||
via.SetWidth(MM(0.8))
|
||||
via.SetLayerPair(F_Cu, B_Cu)
|
||||
via.SetNetCode(nc("GND"))
|
||||
board.Add(via)
|
||||
block_circle(vx, vy, 0.7)
|
||||
# route stub pad -> via
|
||||
unblock_net("GND")
|
||||
path = astar(px, py, vx, vy)
|
||||
if path is None:
|
||||
print(f"!! A* FAILED: GND stub {ref}.{pname}")
|
||||
ok = False
|
||||
else:
|
||||
path_to_tracks(path, "GND")
|
||||
|
||||
# ---- GND pour (bottom) ----
|
||||
z = pcbnew.ZONE(board)
|
||||
z.SetLayer(B_Cu)
|
||||
z.SetNetCode(nc("GND"))
|
||||
z.SetIsFilled(False)
|
||||
ol = z.Outline()
|
||||
for (ox, oy) in [(1.0, 1.0), (BOARD_W - 1.0, 1.0), (BOARD_W - 1.0, BOARD_H - 1.0),
|
||||
(1.0, BOARD_H - 1.0), (1.0, 1.0)]:
|
||||
ol.Append(PX(ox, oy))
|
||||
board.Add(z)
|
||||
|
||||
# ---- edge cuts ----
|
||||
e = pcbnew.PCB_SHAPE(board)
|
||||
e.SetShape(pcbnew.SHAPE_T_RECT)
|
||||
e.SetStart(PX(0, 0))
|
||||
e.SetEnd(PX(BOARD_W, BOARD_H))
|
||||
e.SetLayer(Edge_Cuts)
|
||||
board.Add(e)
|
||||
|
||||
# ---- silk text ----
|
||||
for txt, x, y, sz in [("OSC-MOD v1.0", 23.0, 27.2, 1.2),
|
||||
("J1: COIL", 4.5, 26.2, 0.8),
|
||||
("J2: 1=VCC 2=GND 3=F_OUT", 33.5, 12.5, 0.8)]:
|
||||
t = pcbnew.PCB_TEXT(board)
|
||||
t.SetText(txt)
|
||||
t.SetPosition(PX(x, y))
|
||||
t.SetLayer(F_SilkS)
|
||||
t.SetTextSize(PX(sz, sz))
|
||||
t.SetTextThickness(MM(0.15))
|
||||
board.Add(t)
|
||||
|
||||
board.Save(PCB)
|
||||
print("saved", PCB)
|
||||
print("nets routed OK" if ok else "!!! SOME NETS FAILED !!!")
|
||||
|
||||
# ---- zone fill ----
|
||||
filler = pcbnew.ZONE_FILLER(board)
|
||||
filler.Fill([z])
|
||||
board.Save(PCB)
|
||||
print("zone filled & re-saved")
|
||||
@@ -0,0 +1,250 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Generate KiCad 7 schematic for the standalone oscillator module (osc-module).
|
||||
|
||||
Derived from the full loop-detector schematic (loop-detector.kicad_sch):
|
||||
J1 (coil) -> TVS1 -> T1 (matching xfmr) -> Colpitts osc (Q1 + C1/C2/Cc2)
|
||||
-> LM393 squarer (U1) -> F_OUT with pullup R7 -> J2 (VCC/GND/F_OUT)
|
||||
"""
|
||||
import re, uuid, os
|
||||
|
||||
BASE = os.path.dirname(os.path.abspath(__file__))
|
||||
SYM = os.path.join(BASE, "loopdet.kicad_sym")
|
||||
SCH = os.path.join(BASE, "osc-module.kicad_sch")
|
||||
|
||||
def uid():
|
||||
return str(uuid.uuid4())
|
||||
|
||||
# ---------- extract lib_symbols from loopdet.kicad_sym ----------
|
||||
data = open(SYM, encoding="utf-8").read()
|
||||
pat = re.compile(r'\(symbol "([^"]+)"')
|
||||
sym_blocks = []
|
||||
for m in pat.finditer(data):
|
||||
prefix = data[:m.start()]
|
||||
d = prefix.count('(') - prefix.count(')')
|
||||
if d == 1:
|
||||
start = m.start()
|
||||
depth = 0
|
||||
j = start
|
||||
while j < len(data):
|
||||
if data[j] == '(':
|
||||
depth += 1
|
||||
elif data[j] == ')':
|
||||
depth -= 1
|
||||
if depth == 0:
|
||||
break
|
||||
j += 1
|
||||
sym_blocks.append(data[start:j+1])
|
||||
|
||||
# keep only the symbols the oscillator module needs
|
||||
WANT = {"C", "COMP", "CONN2", "Q_NPN", "R", "TVS_BI", "XFMR"}
|
||||
def top_name(block):
|
||||
m = re.search(r'\(symbol "([^"]+)"', block)
|
||||
return m.group(1) if m else ""
|
||||
kept = [b for b in sym_blocks if top_name(b) in WANT]
|
||||
|
||||
def _prefix(sym_block):
|
||||
return re.sub(r'\(symbol "([^"]+)"', r'(symbol "loopdet:\1"', sym_block, count=1)
|
||||
|
||||
CONN3 = ''' (symbol "loopdet:CONN3"
|
||||
(pin_numbers hide) (pin_names (offset 0))
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(property "Reference" "J" (at -2.54 6.35 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
(property "Value" "J" (at -2.54 -6.35 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
|
||||
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
|
||||
(symbol "CONN3_0_1"
|
||||
(polyline (pts (xy -3.81 -5.08) (xy -3.81 5.08))
|
||||
(stroke (width 0.254) (type default)) (fill (type none)))
|
||||
(circle (center -2.54 -2.54) (radius 1.27)
|
||||
(stroke (width 0.254) (type default)) (fill (type none)))
|
||||
(circle (center -2.54 0) (radius 1.27)
|
||||
(stroke (width 0.254) (type default)) (fill (type none)))
|
||||
(circle (center -2.54 2.54) (radius 1.27)
|
||||
(stroke (width 0.254) (type default)) (fill (type none)))
|
||||
)
|
||||
(symbol "CONN3_1_1"
|
||||
(pin passive line (at -2.54 -2.54 0) (length 1.27)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "1" (effects (font (size 1.27 1.27)))))
|
||||
(pin passive line (at -2.54 0 0) (length 1.27)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "2" (effects (font (size 1.27 1.27)))))
|
||||
(pin passive line (at -2.54 2.54 0) (length 1.27)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "3" (effects (font (size 1.27 1.27)))))
|
||||
)
|
||||
)'''
|
||||
|
||||
lib_symbols = "(lib_symbols\n" + "\n".join(" " + _prefix(b) for b in kept) + "\n" + CONN3 + "\n)\n"
|
||||
|
||||
# ---------- components ----------
|
||||
# (lib, ref, value, x, y, rot)
|
||||
COMPONENTS = [
|
||||
("CONN2", "J1", "接线圈(3~5匝)", 30, 120, 0),
|
||||
("TVS_BI", "TVS1", "TVS", 55, 120, 0),
|
||||
("XFMR", "T1", "1:1 匹配变压器", 85, 120, 0),
|
||||
("C", "C1", "100~470p", 110, 120, 90),
|
||||
("Q_NPN", "Q1", "S9018", 135, 120, 0),
|
||||
("R", "Rc", "2.2k", 145, 116.2, 0),
|
||||
("R", "Rb1", "100k", 131, 111.5, 90),
|
||||
("R", "Rb2", "47k", 131, 128.5, 90),
|
||||
("R", "Re", "1k", 139, 130, 90),
|
||||
("C", "C2", "100p", 145, 125.5, 90),
|
||||
("C", "Cc2", "10p", 153, 116.2, 0),
|
||||
("COMP", "U1", "LM393", 178, 120, 0),
|
||||
("R", "R3", "10k", 158, 114, 90),
|
||||
("R", "R4", "10k", 158, 130, 90),
|
||||
("R", "R7", "10k 上拉", 196, 114, 0),
|
||||
("CONN3", "J2", "VCC/GND/F_OUT", 225, 120, 0),
|
||||
]
|
||||
|
||||
# ---------- wires ----------
|
||||
WIRES = [
|
||||
# coil side: J1 - TVS1 - T1 primary
|
||||
((27.46, 117.46), (77.38, 117.46)), # A: J1.p1 - TVS1.p1 - T1.p1
|
||||
((52.46, 117.46), (52.46, 120)),
|
||||
((27.46, 122.54), (77.38, 122.54)), # B: J1.p2 - TVS1.p2 - T1.p2
|
||||
((57.54, 122.54), (57.54, 120)),
|
||||
# T1 secondary upper: p3 - C1.p1 - base node
|
||||
((92.62, 117.46), (113, 117.46)),
|
||||
((113, 117.46), (113, 120)),
|
||||
((113, 120), (131, 120)),
|
||||
# T1 secondary lower: p4 - C1.p2 - GND
|
||||
((92.62, 122.54), (107, 122.54)),
|
||||
((107, 122.54), (107, 138)),
|
||||
# VCC bus
|
||||
((95, 105), (245, 105)),
|
||||
((145, 116.2), (145, 105)),
|
||||
((131, 108.96), (131, 105)),
|
||||
((158, 111.46), (158, 105)),
|
||||
((193.46, 114), (193.46, 105)),
|
||||
((222.46, 117.46), (222.46, 105)),
|
||||
# GND bus
|
||||
((95, 138), (245, 138)),
|
||||
((131, 131.04), (131, 138)),
|
||||
((139, 132.54), (139, 138)),
|
||||
((145, 128.04), (145, 138)),
|
||||
((158, 132.54), (158, 138)),
|
||||
((222.46, 122.54), (222.46, 138)),
|
||||
# base node
|
||||
((131, 114.04), (131, 125.96)),
|
||||
# collector
|
||||
((139, 116.2), (150.46, 116.2)),
|
||||
((145, 116.2), (145, 122.96)),
|
||||
# emitter
|
||||
((139, 123.81), (139, 127.46)),
|
||||
# comp in+
|
||||
((155.54, 116.2), (170.38, 116.2)),
|
||||
((170.38, 116.2), (170.38, 117.46)),
|
||||
# vref
|
||||
((158, 116.54), (158, 125.96)),
|
||||
((158, 122.54), (170.38, 122.54)),
|
||||
# comp out -> R7 -> J2
|
||||
((185.62, 120), (185.62, 114)),
|
||||
((185.62, 114), (193.46, 114)),
|
||||
((198.54, 114), (222.46, 114)),
|
||||
((222.46, 114), (222.46, 117.46)),
|
||||
]
|
||||
|
||||
# ---------- net labels ----------
|
||||
LABELS = [
|
||||
("VCC", (95, 105), 0),
|
||||
("GND", (95, 138), 0),
|
||||
("VCC", (222.46, 130.54), 0),
|
||||
("GND", (222.46, 134.96), 0),
|
||||
("F_OUT", (222.46, 112.54), 0),
|
||||
]
|
||||
|
||||
# ---------- texts ----------
|
||||
TEXTS = [
|
||||
("振荡模块原理图 — 板框最小版（从环路车检器全图截取）", (20, 20), 3.5),
|
||||
("信号链：线圈 → TVS1 → T1 匹配变压器 → 考毕兹振荡(Q1) → LM393 整形 → F_OUT", (20, 30), 1.5),
|
||||
("接路面环形线圈（3~5匝，双绞屏蔽线 ≤20m）", (20, 100), 1.27),
|
||||
("【设计说明】", (20, 155), 1.5),
|
||||
("1) 本模块仅含振荡+整形部分，供电 VCC 3.3~5V，输出 F_OUT 为方波（频率 = 谐振频率）；", (20, 163), 1.27),
|
||||
("2) 频率计数/判车逻辑由外部 MCU 完成（见主原理图）；", (20, 171), 1.27),
|
||||
("3) R7 为 LM393 开漏输出上拉，必须保留；", (20, 179), 1.27),
|
||||
("4) C1 决定谐振频率 f0 ≈ 1/(2π√(L·C1))，20~150kHz（待现场验证）；", (20, 187), 1.27),
|
||||
("5) TVS1 保护线圈侧浪涌；T1 隔离耦合抗地环路。", (20, 195), 1.27),
|
||||
]
|
||||
|
||||
# ---------- build ----------
|
||||
def fmt_xy(p):
|
||||
return f"(xy {p[0]:g} {p[1]:g})"
|
||||
|
||||
parts = []
|
||||
ROOT_UUID = uid()
|
||||
parts.append("(kicad_sch")
|
||||
parts.append(" (version 20230121)")
|
||||
parts.append(" (generator eeschema)")
|
||||
parts.append(f" (uuid {ROOT_UUID})")
|
||||
parts.append(' (paper "A4")')
|
||||
parts.append(" (title_block")
|
||||
parts.append(' (title "Oscillator Module")')
|
||||
parts.append(' (date "2026-08-24")')
|
||||
parts.append(' (rev "1.0")')
|
||||
parts.append(' (company "xde")')
|
||||
parts.append(' (comment 1 "LC Osc + LM393 squarer, standalone")')
|
||||
parts.append(" )")
|
||||
parts.append("")
|
||||
parts.append(lib_symbols.rstrip("\n"))
|
||||
parts.append("")
|
||||
PINMAP = {
|
||||
"R": ["1", "2"], "C": ["1", "2"], "TVS_BI": ["1", "2"],
|
||||
"Q_NPN": ["B", "C", "E"], "XFMR": ["1", "2", "3", "4"],
|
||||
"COMP": ["+", "-", "OUT"], "CONN2": ["1", "2"], "CONN3": ["1", "2", "3"],
|
||||
}
|
||||
for lib, ref, value, x, y, rot in COMPONENTS:
|
||||
parts.append(" (symbol")
|
||||
parts.append(f" (lib_id \"loopdet:{lib}\")")
|
||||
parts.append(f" (at {x:g} {y:g} {rot})")
|
||||
parts.append(" (unit 1)")
|
||||
parts.append(" (in_bom yes)")
|
||||
parts.append(" (on_board yes)")
|
||||
parts.append(" (dnp no)")
|
||||
parts.append(f" (uuid {uid()})")
|
||||
parts.append(f" (property \"Reference\" \"{ref}\" (at {x:g} {y+6:g} 0) (effects (font (size 1.27 1.27)) (justify left)))")
|
||||
parts.append(f" (property \"Value\" \"{value}\" (at {x:g} {y-6:g} 0) (effects (font (size 1.27 1.27)) (justify left)))")
|
||||
parts.append(f" (property \"Footprint\" \"\" (at {x:g} {y:g} 0) (effects (font (size 1.27 1.27)) hide))")
|
||||
parts.append(f" (property \"Datasheet\" \"\" (at {x:g} {y:g} 0) (effects (font (size 1.27 1.27)) hide))")
|
||||
for pn in PINMAP[lib]:
|
||||
parts.append(f" (pin \"{pn}\" (uuid {uid()}))")
|
||||
parts.append(" (instances")
|
||||
parts.append(" (project \"osc-module\"")
|
||||
parts.append(f" (path \"/{ROOT_UUID}\"")
|
||||
parts.append(f" (reference \"{ref}\") (unit 1)")
|
||||
parts.append(" )")
|
||||
parts.append(" )")
|
||||
parts.append(" )")
|
||||
parts.append(" )")
|
||||
parts.append("")
|
||||
for p1, p2 in WIRES:
|
||||
parts.append(" (wire")
|
||||
parts.append(f" (pts {fmt_xy(p1)} {fmt_xy(p2)})")
|
||||
parts.append(" (stroke (width 0) (type default))")
|
||||
parts.append(f" (uuid {uid()})")
|
||||
parts.append(" )")
|
||||
parts.append("")
|
||||
for name, pos, ang in LABELS:
|
||||
parts.append(" (label")
|
||||
parts.append(f" \"{name}\" (at {pos[0]:g} {pos[1]:g} {ang})")
|
||||
parts.append(" (effects (font (size 1.27 1.27)) (justify left bottom))")
|
||||
parts.append(f" (uuid {uid()})")
|
||||
parts.append(" )")
|
||||
parts.append("")
|
||||
for s, pos, size in TEXTS:
|
||||
parts.append(" (text")
|
||||
parts.append(f" \"{s}\" (at {pos[0]:g} {pos[1]:g} 0)")
|
||||
parts.append(f" (effects (font (size {size:g} {size:g})))")
|
||||
parts.append(f" (uuid {uid()})")
|
||||
parts.append(" )")
|
||||
parts.append("")
|
||||
parts.append(" (sheet_instances")
|
||||
parts.append(' (path "/" (page "1"))')
|
||||
parts.append(" )")
|
||||
parts.append(")")
|
||||
|
||||
out = "\n".join(parts) + "\n"
|
||||
open(SCH, "w", encoding="utf-8").write(out)
|
||||
print("wrote", SCH, len(out), "bytes")
|
||||
@@ -0,0 +1,392 @@
|
||||
(kicad_symbol_lib
|
||||
(version 20220914)
|
||||
(generator "xde")
|
||||
(symbol "R"
|
||||
(pin_numbers hide) (pin_names (offset 0))
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(property "Reference" "R" (at 0 2.54 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
(property "Value" "R" (at 0 -2.54 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
|
||||
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
|
||||
(symbol "R_0_1"
|
||||
(rectangle (start -1.27 -1.27) (end 1.27 1.27)
|
||||
(stroke (width 0.254) (type default)) (fill (type none)))
|
||||
)
|
||||
(symbol "R_1_1"
|
||||
(pin passive line (at -2.54 0 0) (length 1.27)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "1" (effects (font (size 1.27 1.27)))))
|
||||
(pin passive line (at 2.54 0 0) (length 1.27)
|
||||
(name "~" (effects (font (size 1.27 1.27))))
|
||||
(number "2" (effects (font (size 1.27 1.27)))))
|
||||
)
|
||||
)
|
||||
(symbol "C"
|
||||
(pin_numbers hide) (pin_names (offset 0))
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(property "Reference" "C" (at 0 2.54 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
(property "Value" "C" (at 0 -2.54 0) (effects (font (size 1.27 1.27)) (justify left)))
|
||||
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Reference in New Issue
Block a user